This invention relates to a circuit comprising a frequency-determining element, a clock generator for generating a clock signal and a control circuit coupled to the clock generator for generating a control signal as a function of the magnitude of the voltage on the frequency-determining element and for applying the control signal to the frequency-determining element.
Such a circuit is disclosed in the French Patent Application FR-A 2487607. In this prior art circuit an oscillator is biased by the control signal. A second control signal, which is generated by a phase control loop and causes the oscillator signal to be substantially in synchronism with an incoming synchronizing signal, is superposed on this control signal. Since the substantially constant clock signal is used for biasing the circuit, the clock signal is fairly uniform, independent of variations of the supply voltage, and can be dimensioned such that the frequency of the oscillator is approximately in the middle of the lock-in range of the control loop. To that end the control circuit includes an auxiliary oscillator having a rather high frequency and which is incorporated in a control loop, the auxiliary oscillator being controlled to a substantially constant frequency with the aid of a control signal produced in the said control loop as the result of a phase comparison between the clock signal and a signal derived from the signal of the auxiliary oscillator by frequency division. A proportional portion of the latter control signal is the output signal of the control circuit. From the foregoing it will be obvious that the prior art circuit must be rather complicated.